This invention relates to a process for plating through hole vias having high aspect ratios.
Electrical vias allow electrical access to electronic devices or microelectromechanical systems (MEMS) within a package or in a circuit. In order to continually reduce the cost of such packages and circuits, the packing density of devices within the packages and circuits has been continually increased. In order to support the increase in packing density, the pitch between electrical vias for the devices has also continued to shrink. As a consequence, there is a desire to form vias of increasingly large aspect ratio, that is, the vias are tending to become increasingly long and narrow.
Long, narrow vias are often created by plating a conductive material into a hole formed in a substrate. FIG. 1 illustrates a typical prior art process for forming an electrical via by electroplating. A hole 14 is created in a substrate 12 by a directional material removal process such as reactive ion etching (RIE). A seed layer 16 is then deposited conformally over the etched surface, to provide a conductive layer to attract the plating material from the plating bath
Another known method for making vias is to use an anisotropic etch to form the holes with sloping sidewalls, and to deposit the conductive material on the sloped walls of the holes. However, this method often results in conductive material having non-uniform thickness, and the heat conduction in the thin deposited layer is relatively poor. The aspect ratio must also remain near 1:2 (width=2× depth), further limiting the density of the vias.